FFT and FHT engine

ABSTRACT

A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplexer having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT.

BACKGROUND

[0001] Spread spectrum techniques are well known. In a typicalspread-spectrum communication system, transmitted bits are replaced by aspreading sequence, which are stored in a receiver. During transmission,received samples are correlated with the stored sequence to determinethe transmitted bits. For a spread-spectrum system using Walsh Codes,the receiver would typically correlate the received samples with allpossible Walsh Codes of the same length. Such an operation can beefficiently implemented using a Fast Hadamard Transform.

[0002] In another trend, OFDM transmission systems are becomingubiquitous. The major processing elements in an OFDM communicationsystem are the IFFT and FFT blocks at the transmitter and receiver.Considerable processing power and hardware resources are required tocompute the FFT/IFFTs to make the communication system run in real-time.

[0003] FFT and FHT are usually implemented in hardware to meet thereal-time processing requirements for high data throughput communicationsystems. Typically these are implemented as separate hardware blocks.Such separate hardware takes up chip real-estate. Moreover, havingseparate FFT and FHT hardware increases power consumption.

SUMMARY

[0004] In one aspect, a transformation engine includes an addressgenerator; a butterfly unit coupled to the address generator; a twiddleLUT coupled to the address generator; and a multiplexer having a firstinput coupled to the butterfly unit and a second input coupled to thetwiddle LUT.

[0005] Implementations of the above system may include one or more ofthe following. The butterfly unit can compute fast fourier transform(FFT) operations. The butterfly unit can compute decimation in frequencyfast fourier transform (DIF FFT) operations. The butterfly unit can alsocompute fast Hadamard transform (FHT) operations. The twiddle LUTcontains twiddle factors set to one. Input data belonging to FHT samplesare mapped to predetermined inputs. Remaining input data is set to zero.An input buffer can be coupled to the butterfly unit. An output buffercan be coupled to the multiplexer.

[0006] In another aspect, a method for performing a plurality oftransformations includes determining a transformation operation to beperformed on data; and sharing a transformation engine between multipletransformation operations.

[0007] Advantages of the invention can include one or more of thefollowing. The system provides a Fast Hadamard Transform engine that isfast and that shares hardware with other operations in digital radiotransmitters and receivers. By making use of the similarity ofoperations for FFT and FHT it is possible to use the same hardware tocompute FFT and FHT with a small amount of reconfiguration. Formulti-mode communication system, the system supports reusing hardwareblocks of one protocol to perform the computations for other protocolsand thus obviates the need to provide separate hardware blocks. Thissharing reduces chip area and hence the cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 shows a portion of a digital receiver.

[0009]FIG. 2 shows an exemplary FHT topology.

[0010]FIG. 3 shows an exemplary FFT topology.

[0011]FIG. 4 shows an an example of Radix-4 64-point FFT topology beingre-used for FHT

[0012]FIG. 5 shows an exemplary Butterfly re-use pattern of the engineof FIG. 2 to perform FHT processing.

[0013]FIG. 6 shows one embodiment of a FFT/FHT engine.

[0014]FIG. 7 shows an exemplary wireless based system that uses theFFT/FHT engine.

DESCRIPTION

[0015] Reference will now be made in detail to the preferred embodimentsof the invention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the present invention.

[0016]FIG. 1 shows an exemplary receiver circuit 10. The receivercircuit 10 includes a receive filter 20 that receives digitized radiofrequency signals. The filter 20 digitally removes signals outside ofthe receive frequency and provides the filtered data to an engine 30that can handle both FFT and FHT operations. The output of the engine 30is provided to a channel decoder 70.

[0017] FFT is usually used in orthogonal frequency division multiplexing(OFDM) receivers to perform sub-carrier demodulation. Fast Hadamardtransformations are used in spread spectrum systems to de-correlatemultiple codes simultaneously. FFT and FHT both have severalsimilarities that can be exploited. Note the similarities between theRadix-4 FFT operations/topology and the FHT operations/topology used forCCK demodulation. The radix-4 FFT butterfly is given by:$\begin{pmatrix}{X(0)} \\{X(1)} \\{X(2)} \\{X(3)}\end{pmatrix} = {\begin{pmatrix}1 & 1 & 1 & 1 \\1 & {- j} & {- 1} & j \\1 & {- 1} & 1 & {- 1} \\1 & j & {- 1} & {- j}\end{pmatrix}\begin{pmatrix}{x(0)} \\{x(1)} \\{x(2)} \\{x(3)}\end{pmatrix}}$

[0018] A Radix-4 FFT butterly takes in 4 complex inputs and produces 4complex outputs.

[0019] The FHT butterfly takes in two inputs and produces four outputs.$\begin{pmatrix}{X(0)} \\{X(1)} \\{X(2)} \\{X(3)}\end{pmatrix} = {\begin{pmatrix}1 & 1 \\1 & j \\1 & {- 1} \\1 & {- j}\end{pmatrix}\begin{pmatrix}{x(2)} \\{x(0)}\end{pmatrix}}$

[0020] The FHT butterfly takes in two inputs and produces four outputs.By inspection of the matrices, it can be seen that FHT butterfly resultsif x(2)=x(3)=0 in the FFT matrix.

[0021] A 64 point Radix-4 FFT has three stages. Each stage uses 16butterflies. Each stage produces 64 outputs. The total number of inputsamples is 64 and the total number of output samples is 64. The 8pointFHT used in 802.11b has three stages. The first stage has 4 butterflies,the second stage has 8 butterflies and the final stage has 16butterflies. The first stage produces 16 outputs, the second stageproduces 32 outputs and the final stage produces 64 outputs.

[0022] The 64 point Radix-4 FFT takes in 64 complex inputs and produces64 complex outputs, an example of which is shown in FIG. 3, a black-boxview of the 64 point complex FFT. Internally, the operations areperformed using Radix-4 butterflies and the outputs of the butterfliesare multiplied by twiddle factors. As described in more detail below,the circuit of FIG. 6 reduces the area and cost by re-using thecomputation blocks of one receiver for performing the computations forthe other. The FFT engine is reused for FHT by incorporating thefollowing changes:

[0023] 1. Set all twiddle factors equal to 1

[0024] 2. Map the FHT samples to appropriate inputs

[0025] 3. Set the rest of the inputs to zero.

[0026] Turning now to one implementation of the system, a Fast HadamardTransform (FHT) takes in 8 inputs. Here the inputs of the FFT block aredenoted {x0, x1, . . . ,x63}. A set of samples {a0,a1, . . . a7} for FHTis mapped to the FFT inputs {x0, . . . x63} using the following table.The rest of the FFT inputs are set to zero. Input for FHT FFT ports A0X0  A1 X32 A2 X8  A3 X40 A4 X2  A5 X34 A6 X10 A7 X42

[0027] The butterflies of Radix 4 FFT can be re-used for FHT if theintermediate values are properly routed between the butterflies. Thebutterfly re-use pattern for FHT is given in FIG. 5. The circles showbutterflies of the 64-point Radix-4 FFT. The circles in gray are re-usedfor FHT.

[0028]FIG. 2 shows an exemplary Fast Hadamard Transform topology. Thistopology shows ¼th of the structure for a Fast Hadamard transform forinput vector length 8. There are 8 inputs and 16 outputs. The samestructure is repeated 4 times with different values of 2 to obtain the64 output values.

[0029]FIG. 3 shows an exemplary 64-point Radix 4, Decimation inFrequency FFT structure with 64 inputs and 64 output. FIG. 4 shows theapplication of the 64-point Radix-4 FFT structure of FIG. 3 in computinga Fast Hadamard transform for input vector length 8 of FIG. 2. Themapping between the FFT input ports and the FHT input signals is givenin Table 1. The lines in gray indicate the data flow for FHT. It can beseen from the figures that 4 of the FFT butterflies are re-used in thefirst stage, 8 of them in the second stage and 16 of them in the thirdstage. FIG. 5 shows an exemplary butterfly re-use pattern for re-usingthe Radix-4 DIF FFT engine for the computation of FHT. The circlesrepresent the butterflies and the dark circles are re-used.

[0030]FIG. 6 shows the exemplary engine 30 that can be programmablyselected as an FFT engine or an FHT engine. The engine 30 has an inputbuffer 32 that receives data to be processed. The input buffer 32 isdriven by an address generator 34. The output of the input buffer 32 isreceived by a butterfly unit 36. The output of the butterfly unit 36 isprovided to a P/S unit 38. The address generator 34 also drives the P/Sunit 38. The output of the P/S unit 38 is provided to one input of acomplex multiplier 40, while a second input of the complex multiplier 40receives the output of a twiddle LUT 42. The address generator 34 alsodrives the address input of the twiddle LUT 42. The output of themultiplexer is saved in an output buffer 44 whose address input isdriven by the address generator 34. The output of the output buffer 44is presented to the channel decoder 70.

[0031]FIG. 7 shows a block diagram of an exemplary multi-mode wirelessreceiver which implements two protocols for non-simultaneous operation.Protocol 1 uses FFT algorithm for reception and Protocol 2 uses FHTalgorithm. Radio signals are fed to an analog to digital (A/D) converter70 and an A/D converter 90. The output of the A/D converter 70 isprovided to a first receive filter 72, whose output is provided to asynchronizing circuit 74. The output of the synchronizing circuit 74 isprovided to the combined FFT/FHT engine 30 (FIG. 6). The output of theFFT/FHT engine 30 is provided to first and second channel decoders 76and 96, respectively. Correspondingly, the output of the A/D converter90 is provided to a second receive filter 92, whose output is providedto a second synchronizing circuit 94, which in turn drives a secondinput of the combined FFT/FHT engine 30. A digital signal processor 80coordinates and controls the filter, synchronizing circuit, combinedFFT/FHT engine 30, and the channel decoders to provide output data.

[0032] As shown in FIG. 7, separate hardware blocks are used for thefiltering and synchronization operation for these protocols. However,the FFT and FHT block is shown as shared between the protocols thusreducing the hardware requirement. A DSP core controls the operation ofthese hardware blocks. It also selects the mode of operation of thecombined FFT-FHT block.

[0033] Although the invention has been shown and described with respectto certain preferred embodiments, it is obvious that equivalents andmodifications will occur to others skilled in the art upon the readingand understanding of the specification. The present invention includesall such equivalents and modifications, and is limited only by the scopeof the following claims.

What is claimed is:
 1. A transformation engine, comprising: an addressgenerator; a butterfly unit coupled to the address generator; a twiddleLUT coupled to the address generator; and a multiplexer having a firstinput coupled to the butterfly unit and a second input coupled to thetwiddle LUT.
 2. The engine of claim 1, wherein the butterfly unitcomputes fast fourier transform (FFT) operations.
 3. The engine of claim1, wherein the butterfly unit computes decimation in frequency fastfourier transform (DIF FFT) operations.
 4. The engine of claim 1,wherein the butterfly unit computes fast Hadamard transform (FHT)operations.
 5. The engine of claim 4, wherein the twiddle LUT containstwiddle factors set to one.
 6. The engine of claim 4, wherein thetwiddle LUT contains twiddle factors set to one.
 7. The engine of claim4, wherein input data belonging to FHT samples are mapped topredetermined inputs.
 8. The engine of claim 7, wherein remaining inputdata is set to zero.
 9. The engine of claim 1, further comprising aninput buffer coupled to the butterfly unit.
 10. The engine of claim 1,further comprising an output buffer coupled to the multiplexer.
 11. Amethod for performing a plurality of transformations, comprising:determining a transformation operation to be performed on data; andsharing a transformation engine between multiple transformationoperations.
 12. The method of claim 11, farther comprising setting theengine to select the transformation operation.
 13. The method of claim11, further comprising receiving the output of the transformationoperation on the data.
 14. The method of claim 11, wherein thetransformation engine can be selected to perform FFT or FHT operations.15. The method of claim 11, further comprising setting twiddle factorsto one.
 16. The method of claim 11, further comprising mapping inputdata belonging to FHT samples to predetermined inputs.
 17. The method ofclaim 16, further comprising setting remaining input data to zero. 18.The method of claim 11, wherein the transformation engine processesdecimation in frequency FFT.
 19. The method of claim 1, furthercomprising buffering input data and output data.
 20. The method of claim1, further comprising decoding radio frequency channel data from thetransformed data.